SMIC and CXMT Navigate EUV Restrictions Through Costly Workarounds

Chinese semiconductor producers face a difficult calculation as they strive to manufacture cutting-edge silicon without access to the most advanced lithography tools. While export controls have successfully blocked the import of extreme ultraviolet machines from ASML, the industry has not been forced to a standstill. Instead, manufacturers are relying on established deep ultraviolet equipment, a strategy that yields functional products but introduces significant financial and technical complications. The central tension lies in the trade-off between capability and cost, as older machines require more complex processes to achieve similar results.

The reliance on DUV technology stems from its status as the primary bottleneck in China's efforts to close the gap with Western competitors. ASML remains the sole producer of EUV systems, which utilize light with a 13.5nm wavelength to print the finest features on modern processors. Analysts estimate that the disparity in access to this technology has created a lag of five years or more between China and the rest of the world. However, recent developments suggest that the domestic industry has progressed further than many observers anticipated.

Evidence of this progress can be seen in the teardown of Huawei’s Mate 60 Pro, released in 2023, which revealed that the Kirin 9000S processor was fabricated by SMIC using a second-generation 7nm-class process without EUV assistance. More recent examinations of the Kirin 9030 indicate that SMIC has advanced its DUV-based methods to densities approaching those of 5nm manufacturing. Although these achievements are notable, they still trail behind the leading processes employed by TSMC and Samsung.

The underlying technique is known as multiple patterning, where manufacturers break a single intricate layer into several simpler patterns and construct the final design step by step. Chris Mack, co-founder and CTO of Fractilia, argues that the question of whether a chip can be built without EUV often overlooks the associated trade-offs. He notes that industry standards suggest three exposures on a 193 immersion tool carry costs comparable to a single EUV exposure. However, once the process requires four masks, EUV becomes the more economical choice.

Beyond cost, quality presents a significant challenge. Each additional pattern must align perfectly with the previous ones, leading to accumulated overlay errors and process variation. Designers often compensate by adding extra space around features, which increases the overall chip size and reduces the number of usable dies per wafer. Given that wafers can cost tens of thousands of dollars, this reduction in yield is a substantial financial burden. Mack emphasizes that the business model focuses on selling individual dies rather than whole wafers, making efficiency critical.

The memory sector provides a clear illustration of these efficiency gaps. A report from Morgan Stanley in June estimated that CXMT, a Chinese DRAM maker, produces only about one-third as many bits per wafer as its Western counterparts. The bank described access to lithography as a hard ceiling for the development of Chinese memory. Mack also cautioned that process labels like 5nm or 3nm have limited standalone meaning. He noted that while SMIC’s N+3 process represents progress, it remains significantly less scaled than the established 5nm technologies used by Samsung and TSMC.

Despite these constraints, DUV technology still has room for advancement. Micron developed its 1-alpha DRAM without EUV, utilizing multiple patterning and precise process control, a feat Mack described as pushing 193 immersion farther than other memory manufacturers have done. Morgan Stanley believes CXMT’s planned transition to 1-alpha DRAM for HBM3e is feasible without EUV. Douglas Fuller, a researcher at Copenhagen Business School, anticipates that advanced packaging will allow firms to utilize DUV for the latest DRAM generations by the end of the decade.

However, the limitations of DUV become more apparent at smaller nodes. Micron eventually adopted EUV for its 1-gamma DRAM, claiming a bit density improvement of over 30% compared to the previous generation. While EUV has its own issues, such as stochastic effects that require higher exposure doses, Mack stated that he would be hard pressed to believe 3nm or 2nm nodes could be economically viable without it. He added that if China had the full 193 immersion ecosystem and designed products around it, it could go a long way, though he stressed that memory is much easier to manage than logic.

Chinese chipmakers are unlikely to stall despite these challenges. They can continue to push DUV technology while accepting larger dies, lower yields, or longer manufacturing times, and they can expand capacity. Morgan Stanley projects that CXMT will maintain its position on 1-alpha without EUV but will increase its share of global DRAM bit supply from 14% in 2026 to 16% in 2028 through new greenfield capacity. The bank also expects China’s self-sufficiency in AI chips to rise from 42% in 2025 to 70% by 2030, although gaps in EUV, HBM, and advanced software will likely persist.